Query by String word spotting based on character bi-gram indexing

In this paper we propose a segmentation-free query by string word spotting method. Both the documents and query strings are encoded using a recently proposed word representa- tion that projects images and strings into a common atribute space based on a pyramidal histogram of characters(PHOC). These attribute models are learned using linear SVMs over the Fisher Vector representation of the images along with the PHOC labels of the corresponding strings. In order to search through the whole page, document regions are indexed per character bi- gram using a similar attribute representation. On top of that, we propose an integral image representation of the document using a simplified version of the attribute model for efficient computation. Finally we introduce a re-ranking step in order to boost retrieval performance. We show state-of-the-art results for segmentation-free query by string word spotting in single-writer and multi-writer standard datasetsComment: To be published in ICDAR201

250 MHz Multiphase Delay Locked Loop for Low Power Applications

Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provides a high locking range with less phase noise and jitter due to differential pair configuration.For increasing the acquisition range and locking speed of the DLL, modified true single phase clock (TSPC) based phase frequency detector is used. The proposed design is implemented at 0.18 um CMOS technology and at power supply of 1.8V . It has power consumption of 1.39 mW at 125 MHz center frequency with locking range from 0.5 MHz to 250 MHz

Design of Low Voltage Improved performance Current Mirror

This paper proposes a low voltage current mirror circuit with low input impedance and high output impedance. These improvements are obtained by adding an amplifier which provides biasing voltage to the transistors. Its operation and results are compared with conventional and cascode current mirror circuits. The circuits are designed using Tanner EDA Tool in 90nm CMOS technology with 0.8V supply voltage. Simulation results shows that the minimum output voltage is reduced to 0.1 V, also input resistance is reduced to 0.179k? and consumes only 46µW power. Keywords: Current mirror, Input resistance Output resistance, Input compliance voltage, Output compliance voltage

Graph Coloring via Degeneracy in Streaming and Other Space-Conscious Models

We study the problem of coloring a given graph using a small number of colors in several well-established models of computation for big data. These include the data streaming model, the general graph query model, the massively parallel computation (MPC) model, and the CONGESTED-CLIQUE and the LOCAL models of distributed computation. On the one hand, we give algorithms with sublinear complexity, for the appropriate notion of complexity in each of these models. Our algorithms color a graph $G$ using about $\kappa(G)$ colors, where $\kappa(G)$ is the degeneracy of $G$: this parameter is closely related to the arboricity $\alpha(G)$. As a function of $\kappa(G)$ alone, our results are close to best possible, since the optimal number of colors is $\kappa(G)+1$. On the other hand, we establish certain lower bounds indicating that sublinear algorithms probably cannot go much further. In particular, we prove that any randomized coloring algorithm that uses $\kappa(G)+1$ many colors, would require $\Omega(n^2)$ storage in the one pass streaming model, and $\Omega(n^2)$ many queries in the general graph query model, where $n$ is the number of vertices in the graph. These lower bounds hold even when the value of $\kappa(G)$ is known in advance; at the same time, our upper bounds do not require $\kappa(G)$ to be given in advance.Comment: 26 page

Design of Low Offset and High Speed CMOS Comparator for Analog to Digital Converter

In today’s world everything is digitized but nature is analog, so it is necessary to have such a device which converts analog signal into digital and for this analog to digital converter is required. Now a day’s ADC’s require lesser power, better slew rate, high speed and less offset. Performance limiting component for ADC’s are amplifiers and comparators in which comparator is the most important.This paper presents the design of low offset low power dissipation and high speed  comparator. The proposed comparator consists of a preamplifier stage, decision stage and self biased output buffer stage. The proposed design uses a low power current mirror circuitry for providing a highly biased current. The circuit is designed using 90nm CMOS process for a supply voltage of 1V and reference voltage of 0.5V and power consumption is approximately 300?W. Keywords: CMOS Comparator, Current Mirror, Pre Amplifier, Output Buffe

Learning Cross-Modal Deep Embeddings for Multi-Object Image Retrieval using Text and Sketch

In this work we introduce a cross modal image retrieval system that allows both text and sketch as input modalities for the query. A cross-modal deep network architecture is formulated to jointly model the sketch and text input modalities as well as the the image output modality, learning a common embedding between text and images and between sketches and images. In addition, an attention model is used to selectively focus the attention on the different objects of the image, allowing for retrieval with multiple objects in the query. Experiments show that the proposed method performs the best in both single and multiple object image retrieval in standard datasets.Comment: Accepted at ICPR 201

Design of Ultra Low Power Integrated PLL using Ring VCO

The design of an ultra low power Phase Locked Loop (PLL) is presented in this paper. The proposed PLL consists of a phase detector, a charge pump, low pass filter, and a ring oscillator based voltage controlled oscillator (VCO). The performance of Voltage Controlled Oscillator is of great importance for PLL. The circuit is designed using 0.13µm CMOS technology with the supply voltage of 1V and has a power consumption of 254µW. Keywords: Charge Pump, CMOS Technology, Low Pass Filter, Phase Detector, Phase Locked Loop, Voltage Controlled Oscillator